1. Field of the Invention
This invention relates to an apparatus for displaying an image in a reduced scale, and more particularly to an image reduction apparatus which reduces an interlace video signal such as an NTSC (National Television System Committee) signal or a PAL (Phase Alternation Line) signal.
2. Description of the Related Art
An exemplary construction of conventional image reduction apparatus is shown in FIG. 4. Referring to FIG. 4, the image reduction apparatus includes a horizontal sampling circuit 12, a horizontal address counter 13, a vertical sampling circuit 14, a vertical address counter 15, a write control circuit 16 and a frame memory 17.
Operation of the image reduction apparatus where the reduction rate is set to 2/3 is illustrated in time charts of FIGS. 5 and 6. In particular, FIG. 5 illustrates the operation when a video signal is reduced in a horizontal direction while FIG. 6 illustrates the operation when a video signal is reduced in a vertical direction. Referring to FIGS. 4 to 6, the horizontal sampling circuit 12 starts a sampling operation of a clock signal 111 when a horizontal, pixel signal 112 changes over to a HIGH level, and outputs a horizontal sampling signal 113 in accordance with a preset horizontal reduction rate in synchronism with the clock signal 111. The vertical sampling circuit 14 starts a sampling operation of a horizontal synchronizing signal 115 when a vertical pixel signal 116 changes over to a HIGH level, and outputs a vertical sampling signal 117 in accordance with a preset vertical reduction rate in synchronism with the horizontal synchronizing signal 115.
The horizontal address counter 13 increments its count value by one when the clock signal 111 rises while the horizontal sampling signal 113 remains at a HIGH level, but resets its count value to zero when the horizontal synchronizing signal 115 changes over to a LOW level. An output 114 of the horizontal address counter 13 designates a horizontal address of the frame memory 17.
The vertical address Counter 15 increments its count value by one when the horizontal synchronizing signal 115 rises while the vertical sampling signal 117 remains at a HIGH level, and outputs a value twice its count value with the LSB (Least Significant Bit) thereof set to "0" when a vertical synchronizing signal 121 is at a LOW level (first field), but outputs a value twice its count value with the LSB thereof set to "1" when a field change-over signal 122 is at a HIGH level (second field). An output 118 of the vertical address counter 15 designates a vertical address of the frame memory 17.
The write control circuit 16 outputs a write signal 119 for writing image data 120 into the frame memory 17 when the horizontal sampling signal 113 is at a HIGH level and the vertical sampling signal 117 is at a HIGH level.
With the conventional image reduction apparatus of FIG. 4, however, since the vertical sampling circuit 14 repeats a same operation for each vertical synchronizing signal, same lines in the first field and the second field are sampled out, and in the case of a non-interlace image, two successive lines are sampled out or abandoned. The manner Just described is illustrated in FIG. 7. Referring to FIG. 7, in this instance, the vertical reduction rate is 2/3, and a line sampled out is indicated by X. The second line (D2L), the fifth line (D5L), the eighth line (D8L), . . . in the first field and the second line (E2L), the fifth line (E5L), the eighth line (ESL), . . . are sampled out and the remaining data are written into the frame memory 17. When read out and display of the data in a non-interlaced relationship from the frame memory 17 occurs, the data are read out in order of D0L, E0L, D1L, E1L, D3L, E3L, D4L, E4L, D6L, E6L, . . . while individual two successive lines of D2L and E2L, DSL and E5L, . . . are sampled out. Accordingly, there is a problem in that the discontinuity at such sampled out portions degrades the picture quality.